In what way can I accurately measure the amount of CICS transaction delay attributable to region dispatch time in an MRO environment with restricted processor availability?
Among the ambient workload on the box, we have 5 active CICS regions competing for 2 logical processors. I see a lot of evidence that tends to point to region dispatch time as a big component of what gets charged to MRO wait. But I've not unearthed the 'smoking gun'. Any ideas?
From the sounds of it, you can do all the investigation you like, but I bet it will come down to the fact that you require some more processor resource for your environment!
I think the reason why you are pointing the finger at MRO activity, is that there are more opportunities for MVS waits to occur in this code (as it uses a lot of Cross-Region, Shared MVS Memory and other MVS function via the SVC) than in the rest of CICS. Thus, when you are processor constrained, these waits are the most likely places for the OS/Hardware to take the opportunity to direct the CPU elsewhere and so additional wait time comes up in the stats.
In a different environment, I would expect extra time to be allocated to VSAM activity - for similar reasons.
So I would not bother to turn on full Stats/Monitoring and do an extensive analysis : as I don't think you would come up with a different answer to what you have (correctly in my opinion) already deduced.
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