The latest edition of IBM's mainframe architecture, the zEnterprise EC12, was recently unveiled. As with each...
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successive model, it is bigger, faster and cheaper, so let's open it up and see what's changed.
The zEC12's processor clock speed, a closely watched yet ultimately misleading indication of CPU power, is 5.5 GHz, a modest increase from the 5.2 GHz of the z196. But, IBM warns us, they are approaching the limits of present technology, which makes great leaps in speed more difficult to obtain. Instead, IBM put its effort into redesigning other elements of the machine.
The zEC12 sports six processors to a chip, so a fully loaded central processing complex (CEC) contains 101 customer-configurable engines. Thus, the biggest zEC12 model delivers more than 78,000 millions of instructions per second (MIPS), 50% more than an M80 z196 with the same data center footprint. As in previous processor generations, IBM added new instructions that appear to be aimed at boosting Java performance.
IBM redesigned the instruction pipeline to do a better job with out-of-order instruction execution. To keep the pipeline fed, IBM increased the size of Level 1 (L1) and L2 core cache. With six processors on each chip sharing L3 cache, HiperDispatch has better chances of preserving memory locality of reference and improving cache use. L4 cache is at the book level and can be shared between books. The maximum amount of central storage, just over 3 TB of redundant array of independent memory (RAIM), remains the same as the z196's mainframe architecture.
Z Blade Extension (zBX) users will need to upgrade to a model 003 because the zEC12 will not talk to earlier models.
"Books" inside the mainframe
Internally, mainframes are arranged into books. Each book has a set of chips, processors, memory, cache and other hardware. If a machine has more than one book, they're connected on a memory bus.
Communication within a book is faster than without since all the processors in a book can share the L4 cache. It also means the processors in a book have faster access to data in cache than if they have to get it somewhere else.
IBM delivers books with the total number of available processors, and microcode controls how many of them are available to customers.
External water cooling is still optional. Otherwise, the zEC12 uses a closed loop system that circulates water through an air-cooled radiator. The radiator and the ability to run cables through the top of the box enable the zEC12 to sit on a nonraised floor.
IBM provides toleration program temporary fixes (PTFs) for z/OS 1.10 and 1.11 while exploitation requires release 1.12 or above. There will be PTFs for C++ to enable application code to exploit the new processor through compiler options ARCH(10) and TUNE(10).
Besides the processor, here are some other new features:
Transaction Execution Facility (TEF): TEF, IBM's implementation of transactional memory, is supposed to simplify the serialization of storage objects, thus allowing programmers to write parallel processes without traditional techniques like enqueues, locks or latches. At this point it's difficult to know the specifics of IBM's implementation, but the company says Java will be the first language to support this feature.
Flash Express: Flash memory has recently made a splash in distributed systems as a high-performance alternative to disk storage. The new mainframe supports flash memory mounted in the I/O tray. At this time, the biggest exploiters appear to be Real Storage Manager (RSM) and Dump services. RSM can use the flash for pageable 1 GB and 2 GB pages. This benefit extends to subsystems that support 1 GB pages, such as IMS and DB2. Dump services uses flash memory to capture diagnostic data more quickly and with less stress to the ongoing workloads.
zAware: zAware is probably the most interesting of the new developments. It is an out of band mainframe monitor that runs as firmware in a separate logical partition (LPAR). IBM designed zAware to read system logs and "learn" what's normal in the customer's sysplex. After kibitzing the logs, zAware becomes wise enough to notice when a message or set of messages come out at an odd time, as well as messages that don't come out at all. In the tradition of "big data," it also has a WUI for searches and graphs. zAware remembers what it learned and will need some direct access storage devices (DASD) dedicated to it. Also note that it is separately ordered and paid for, not bundled with the zEC12.
Should I buy one?
Because the new processors' footprint effectively matches older models, customers just about to outgrow their z196es can buy zEC12s for additional computing capacity without adding to the size of the data center. Even z196 customers that aren't near their limit may want to consider buying a zEC12 to take advantage of its 60 subcapacity settings that allow finer tuning of capacity to demand.
One motivation for customers with older or mixed processor fleets is that the introduction of the zEC12 and IBM's N-2 rule -- a processor cannot interoperate with another machine more than two generations older than itself -- just rendered z9s obsolete. In addition, the zEC12 announcement mentions some changes to Advanced Workload License Charges (AWLC) through the use of entitlements called Technology Transition Offerings, which sounds like an option for easing customers off of the old technology. IBM may also be willing to offer good money for older processors to eliminate competition on the used market. Lastly, just like shopping for a car, prices may be better toward the end of a quarter.
The usefulness of some of the new features depends on the data center. A real storage-constrained environment may need to take advantage of flash memory and the larger pages. Similarly, installations that value availability will want to exploit IBM's zAware.
Or, to put it succinctly, the "I" in IBM stands for "it depends."
ABOUT THE EXPERT: Robert Crawford has been a systems programmer for 29 years. While specializing in CICS technical support, he has also worked with VSAM, DB2, IMS and other mainframe products. He has programmed in Assembler, Rexx, C, C++, PL/1 and COBOL. The latest phase in his career finds him an operations architect responsible for establishing mainframe strategy and direction for a large insurance company. He works in south Texas where he lives with his family.