About six weeks ago, AMD started shipping Barcelona following a stumble due to an errata the company found and corrected before shipping the product en masse. The processor was supposed to ship in the second half of 2007.
Up next is Shanghai, AMD's first 45-nm quad-core processor. Shanghai is on track for production in the second half of this year and will feature HyperTransport 3.0 technology, a low-latency, high-speed link for processor-to-processor communication. It will also have three times the Level 3 cache of Barcelona, which is a 65-nm quad-core processor with 2 MB Level 3 cache. Shanghai will also run at idle levels 20% less than that of Barcelona and will have 10% more bandwidth support than Barcelona.
In the second half of 2009; Istanbul will follow, a six-core processor based on the same chipset and platform (Socket F) as Barcelona and Shanghai. It will also be a native processor (with all six cores on one piece of silicon), and like Shanghai, it will be a 45-nm processor with 6 MB of Level 3 cache and will use DDR2, or dual-channel, memory.
As is par for the current course, Santa Clara, Calif.-based Intel Corp.plans to release a six-core 45-nm processor on a single die, code-named Dunnington about a year ahead of AMD at the tail end of this year.The 12-core processor
In the first half of 2010, though, the game changes. AMD plans to leap from six cores directly to 12 with a processor code-named Magny-Cours, skipping the eight-core processor altogether.
At that time, Intel expects to have an eight-core processor available with Nehalem.
The jump from six cores directly to 12 shouldn't pose problems for application developers, who, as SearchDataCenter.com has reported previously , are trying to catch up with processor development. And processor and server companies are doing everything they can to help get developers up to speed, said Charles King an analyst at Pund-IT Inc..
"IBM and Intel have been supporting multicore developer projects, and Sun has been aiding efforts around its multithreaded Niagara processors," King said. "AMD's decision to move to six- and 12-core designs may look a bit odd now, but by the time those chips make it to market I expect developers will be in a much better position to take advantage of their capabilities."
AMD's 12-core processor will be based on a new, third-generation AMD Opteron processor Socket G34 platform. It will be the marriage of two six-core processors stuck together – which AMD said it could not have done effectively with its dual-core processors to create quad-core, which Intel did, said Randy Allen, corporate vice president and general manager of AMD's server and workstations.
This is significant, because AMD has highlighted the fact that its quad-core processor is "native" -- that is, all four cores sit on one piece of silicon -- to differentiate it as superior compared with its competitor, Intel. Allen explains that sticking two six-core processors together to make a 12-core was possible because of advancements in technologies.
"With our quad-core Barcelona, we rejected the idea of putting two dual-cores together, because the performance would not have been what it is with a native processor. Intel went ahead with that scenario, and we believe they made some mistakes with that," Allen said. "With Magny-Cours, we found we could use two separate pieces to add features and meet near-mono-processor performance."
The Magny Cours processor – a code-name based on a Formula One racing site, like all of AMD's code names – will be a 45-nanometer processor with 12 MB of Level 3 cache, based on the new Maranello platform, which will use DDR-3 memory and include HyperTransport 3.0 and the virtualization technology, AMD-V, like its predecessors.
When Magny Cours hits the market, so will another six core processor code-named "Sao Paulo," based on the same new platform and chipset as Magny Cours, with DDR3 memory and HyperTransport capabilities.
Let us know what you think about the story; email Bridget Botelho, News Writer.
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